module perireg
	(
	 clock, resetn, load, sclr,
	 PERIADDR, PERICTRL, PERIVAL,
	 PERIADDRREG, PERICTRLREG, PERIVALREG
	);
input			clock, resetn;
input			load, sclr;
input	[3:0]	PERIADDR;
input	[7:0]	PERICTRL;
input	[15:0]	PERIVAL;

output	[3:0]	PERIADDRREG;
output	[7:0]	PERICTRLREG;
output	[15:0]	PERIVALREG;

reg		[3:0]	PERIADDRREG;
reg		[7:0]	PERICTRLREG;
reg		[15:0]	PERIVALREG;

always @(posedge clock or negedge resetn)
begin
	if (!resetn)
	begin
		PERIADDRREG <= 0;
		PERICTRLREG <= 0;
		PERIVALREG <= 0;
	end
	else if (sclr)
	begin
		PERIADDRREG <= 0;
		PERICTRLREG <= 0;
		PERIVALREG <= 0;
	end
	else if (load)
	begin
		PERIADDRREG <= PERIADDR;
		PERICTRLREG <= PERICTRL;
		PERIVALREG <= PERIVAL;
	end
end
endmodule